The present invention relates to an improved method for erasing and writing information in an electrically alterable memory, and more particularly to a method of erasing and writing information in an electrically erasable programmable read only memory ("EEPROM").
We have discovered a unique solution to the "program disturb" problem in memory cells such as those in current P-channel EEPROM structures. Program disturb occurs when there is a write or erase to a selected group of cells in an array, and the state or content of other, non-selected cells, which is supposed to be left unchanged, is unintentionally changed. The program disturb of such other, non-selected cells may not occur as a result of one programming cycle. The unwanted change may occur incrementally and gradually over many (even millions of) programming cycles. The program disturb problem can be quite subtle and difficult to observe, but can be severely limiting for some applications of the cell.
We use the nomenclature for electrical operations performed upon an array of memory cells in a slightly different manner than typically occurs. We use here the term "write" to refer to an operation of placing electrons onto a floating gate. We use the term "erase" to refer to an operation of removing electrons from a floating gate. The term "program" as used here refers to one cycle of cell programming, which includes a write operation and an erase operation.
In addition, because of the need to densely pack memory cells, electrical isolation between adjacent columns of cells in a byte of cells being erased is a concern. Columns of cells must be spaced to maintain an acceptable level of electrical isolation.
This invention represents an improvement upon the structure and operation described in U.S. Pat. No. 5,790,455, "Low Voltage Single Supply CMOS Electrically Erasable Read-Only Memory," in U.S. Pat. No. 5,986,931, "Low Voltage Single CMOS Electrically Erasable Read-Only Memory," and in U.S. patent application Ser. No. 09/262,675, and entitled "Independently Programmable Memory Segments within a PMOS Electrically Erasable Programmable Read Only Memory Array Achieved by N-well Separation and Method Therefor," Filed Mar. 19, 1999, and assigned to the same assignee as the present application. Based on these two patents and application, the following summarizes the overall structure of an EEPROM memory array and the voltages applied to it during the write and erase operations.
The program disturb problem occurs because groups of cells share a number of common connections, including: a bit line, a word line, a source line, and an N-well. However, cells need to share these connections in order to make the memory array compact and to reduce the number of signal lines routed into it. Electrical isolation between adjacent memory cells is a concern because it is necessary to place adjacent cells as close to one another as possible to make the array compact. So, an understanding of the structure and operation of a current memory array is important to understanding how the disturb problem and electrical isolation problem become manifest and how the present invention addresses these two problems.
FIG. 1 is a circuit schematic diagram of a p-channel memory cell, which will be referred to as the PEEC cell (p-channel EEPROM Cell). FIG. 2 is a schematic cross-section diagram of the PEEC cell, along the channel of the FIG. 1 device and in a direction parallel to the bit line. By comparing FIGS. 1 and 2, a correspondence can be seen between the various symbolic representations of the cell components in FIG. 1 with their physical embodiment in the cross-section of FIG. 2. For example, the source and drain of the cell are represented by simple lines on either side of the word line in FIG. 1 and these are actually p-type diffusions in an n-well shared by many memory cells as depicted in FIG. 2. In fact, each source and drain diffusion is actually shared by two adjacent cells. The "fragments" of poly 2 to the left and right of the poly 2 word line of the cell in the center of the diagram indicate this. In FIG. 1, it can be seen that there are four terminals to the cell: (1) the poly 2 word line that is shared by a row of cells, (2) the source that is connected to the metal source line, (3) the drain that is connected to the metal bit line, and (4) the N-well body that is a region of n-type silicon shared by several columns of cells. Physically, the metal bit line and source line run parallel to each other in pairs down each column of the array. Each column of cells has one bit line and one source line.
In FIG. 2, the cross-section is along and through the bit line so the metal line is visible in the cross-section. The metal source line and its contact to the source p+ region is not visible in FIG. 2 because it is parallel to the bit line and out of the plane of the paper. FIG. 1 also indicates where voltages are applied to the PEEC cell to program or read the cell information. These voltages are labeled V.sub.BL (the voltage on the bit line), V.sub.NW (the voltage on the shared N-well region), V.sub.SRC (the voltage on the source line), and V.sub.WL (the voltage on the word line).
FIG. 3 is a schematic diagram of a portion of a large memory array. An N-well region is depicted as a dashed line box surrounding a large group of memory cells. In the figure, two N-wells, labeled N-well #0 and N-well #1, are shown. N-well #0 contains eight complete columns of cells. N-well #1 would normally also contain eight columns of cells, but only 4 columns are shown due to space limitations in the figure. Eight columns are shown as being contained in one N-well because this is the typical size of a "byte" or "word" of information. One "byte" or "word" would actually be the number of cells along the intersection of one word line with the number of columns in one N-well. Thus, one N-well contains many bytes or words, corresponding to the many word lines that cross the N-well. However, any number of columns could be contained in a single N-well (i.e. the "byte" or "word" size could be 14, 16, 32, or any number desired for the product). Also, there could be any number of N-well segments in the large array. Only two are shown because this is sufficient for the present description.
In FIG. 3, only the top four and last two rows of cells (word lines) are shown due to space limitations. In this figure, it is assumed that there are n+1 word lines, numbered from 0 through n. The number n could be only a few, or it could be hundreds or thousands. The schematic diagram for one PEEC cell that appears in FIG. 1 can be seen repeated many times in the array depicted in FIG. 3. Cells in the same column share a bit line, a source line, and the N-well (note the three parallel lines running down each column). Cells in the same row share a word line (note the single horizontal line running along each row). All cells in the array are identified individually by the notation, M.sub.x,y, where x=the row number and y=the column number.
At the bottom of each column, the last transistor is not a PEEC cell, but a source select transistor, denoted by the notation Q.sub.z,y, where z=the N-well number and y=the column number. The source select transistor is, as taught in the prior art patents, used at the bottom of each column to separate the column source lines during the erase operation. Otherwise the undesirable condition of having the programming high voltage signal shorted to ground could occur. The source select transistor must be turned on to read a cell and off during the erase part of a programming cycle. This is accomplished by the line running left to right which connects all of the source select transistor gates, and has the voltage label at its terminus, V.sub.sel. When the source select transistor is turned on, it connects the voltage, V.sub.src, which is connected to all the source select transistors to the source lines. The voltages applied to the N-wells are labeled, V.sub.NW0 and V.sub.NW1. The voltages applied to the word lines are labeled, V.sub.WL0, V.sub.WL1, . . . , V.sub.WLn. The voltages applied to the bit lines are labeled, V.sub.BL0, V.sub.BL1, and so on. Many commercial products, such as "byte-selectable" or "full-featured" EEPROM memories, select and program only one byte of cells at a time, leaving all other bytes in the array unaltered. This feature is assumed in the following discussion.
The above-noted U.S. patent application discloses segmentation of N-wells so as to separate the cells along each word line into individually programmable bytes. The above-noted patents specify the voltages applied to cells in the N-well containing the byte to be programmed, but do not specify the voltages to be applied to memory cells in deselected (i.e., non-selected) N-wells. The voltages applied to the deselected N-wells and their associated bit lines are specified in the above-noted U.S. patent application.
In the memory cells described above, the write operation places electrons onto the floating gate of the memory cells being written. This causes a shift in the memory transistor threshold voltage to a low negative or perhaps a positive value. The merged select transistor in the cell prevents the overall cell threshold from becoming a positive value, however. The result of the write operation is that a cell becomes conductive during a subsequent read operation.
FIG. 4 is a schematic diagram corresponding to that of FIG. 3, but with the voltages that would be applied to execute a "write" operation of the target byte of cells enclosed by the bold rectangle. After executing the "write" the cells in the target byte would be placed into the conductive state during a subsequent read operation. All other bytes of cells in the array, termed "deselected" bytes, are intended to be left unaltered, the electronic charge stored on their floating gates being unchanged. The N-well of the byte to be written, N-well #0 in the example shown in the figure, is set at 0V and the N-wells of all other bytes which are deselected (unselected and not to be changed) are set at the programming voltage, Vpp. Vpp is the "high voltage" used in programming operations and typically lies in the range of 12 to 20V. The word line of the byte to be written is set at Vpp, and all unselected bytes have their word lines set at 0V. All bit lines are set to 0V. The source select line has V.sub.sel &gt;=0V and the source line has V.sub.src =0V. The source select transistors are all p-channel enhancement devices, meaning that they must have a gate-source voltage, V.sub.gs, which is more negative than the threshold voltage, V.sub.tp, of the device in order for their channels to be on ,i.e., conduct. The voltage conditions applied in the write operation cause the source select transistors of the selected byte (Q.sub.0,0 through Q.sub.0,7) to be non-conductive or off. Thus all of the source lines in the selected N-well (#0) are floating. The source select transistors in the unselected N-wells may be on or off, depending upon the exact value of V.sub.sel. In any case, it is not critical whether these source select transistors are on or off and whether the source lines are floating or connected to 0V. The results for the write operation will be the same.
Since the memory cells and source select transistors in the deselected N-wells share the signal lines running horizontally in the array (e.g. the word lines) with the cells in the selected N-well (in FIG. 4, N-well #0), they must have their voltages set so as not to cause a change in the stored charge on the deselected or unselected memory cells. The word line voltage of the byte that is being written is at Vpp with the selected N-well at 0V in order to cause electrons to tunnel through the thin dielectric layer between the N-well and floating gate. This requires all deselected N-wells to have Vpp applied to them to avoid also writing the cells along the same word line (e.g. cells M.sub.0,8 through M.sub.0,11 in FIG. 4). The deselected word lines have 0V applied to them over the selected N-well to avoid writing the unselected cells. For cells in the deselected N-wells that receive Vpp, these same word lines have 0V. Thus the bit lines of the cells in the deselected N-wells must have 0V applied to them to avoid changing the charge on their floating gates. An example of one such cell is M.sub.1,8. Its N-well is at Vpp and its word line is at 0V, causing the cell channel to be in inversion. With the bit line of this cell set to 0V, however, the inversion layer of charge present in the cell channel under the floating gate is also set to 0V since it is connected electrically to the bit line via the drain p-type diffused region. Thus the potential difference applied between the word line and inversion layer under the floating gate is 0V, and no inadvertent programming should occur.
The erase operation removes electrons from the floating gates of the cells being erased, giving them a high negative threshold voltage and causing them to be in the non-conductive state when read. FIG. 5 is a schematic diagram corresponding to FIG. 3, but with voltages applied for an erase operation. As with FIG. 4, a target byte is enclosed in a bold line rectangle. Unlike the write operation in which all cells in the target byte are set to the same predetermined state, the erase operation only erases cells in the target byte that are desired to be in the non-conductive state. The erase operation leaves the other cells in the target byte in the conductive state. This allows impressing a "bit pattern" into the byte of cells, with some in the binary "0" state and some in the binary "1" state. As noted above, a programming cycle includes writing all of the cells to a predetermined state (e.g., a conductive state) and then selectively erasing some of the cells to a non-conductive state, leaving the others unchanged. Only cells with their bit lines set to Vpp in the erase operation will be erased, those with bit lines set to 0V will be left in the written state. In the example shown in FIG. 5, only cells M.sub.0,0 and M.sub.0,2 will be erased in the target byte. The target byte has its N-well set at Vpp and its word line set at 0V. Deselected word lines are set at Vpp and V.sub.sel =Vpp, so that all source select transistors are off and all source lines are disconnected from V.sub.src. Comparing FIGS. 4 and 5, it can be seen that the deselected N-wells (N-well #1) and their associated bit lines have the same voltages applied in the erase operation as in the write operation. The main difference these deselected cells see is a reversal of the word line voltages with the word line of the target byte set to 0V instead of Vpp and the deselected word lines set to Vpp instead of 0V. The same approach to preventing unwanted erasing of the cells in these deselected N-wells as for a write operation applies to the erase operation as well. It should be noted that all of the above is discussed in U.S. Pat. No. 5,986,931 (in particular, FIG. 21, table 8 and text column 22 of the patent). That Patent does not disclose the voltages applied to the deselected N-wells (for example, N-well #1 in FIG. 4) and the bit lines contained within them.
The read operation involves applying only low voltages to the array to detect which memory cells are conductive and which are non-conductive. The details of reading the cell are well known and not important for an understanding of the present invention.